RDNA 4

RDNA 3

Architecture

Chiplet packaging

For the first time ever in a consumer GPU, RDNA 3 utilizes modular chiplets rather than a single large monolithic die. AMD previously had great success with its use of chiplets in its Ryzen desktop and Epyc server processors. The decision to move to a chiplet-based GPU microarchitecture was led by AMD Senior Vice President Sam Naffziger who had also lead the chiplet initiative with Ryzen and Epyc. The development of RDNA 3's chiplet architecture began towards the end of 2017 with Naffziger leading the AMD graphics team in the effort. The benefit of using chiplets is that dies can be fabricated on different process nodes depending on their functions and intended purpose. According to Naffziger, cache and SRAM do not scale as linearly as logic does on advanced nodes like N5 in terms of density and power consumption so they can instead be fabricated on the cheaper, more mature N6 node. The use of smaller dies rather than one large monolithic die is beneficial for maximizing wafer yields as more dies can be fitted onto a single wafer. Alternatively, a large monolithic RDNA 3 die built on N5 would be more expensive to produce with lower yields.

RDNA 3 uses two types of chiplets: the Graphics Compute Die (GCD) and Memory Cache Dies (MCDs). On Ryzen and Epyc processors, AMD used its PCIe-based Infinity Fabric protocol with the package's dies connected via traces on an organic substrate. This approach is easily scalable in a cost-effective manner but has the drawbacks of increased latency, increased power consumption when moving data between dies at around 1.5 picojoules per bit, and it cannot achieve the connection density needed for high-bandwidth GPUs. An organic package could not host the number of wires that would be needed to connect multiple dies in a GPU. data

RDNA 3's dies are instead connected using TSMC's Integrated Fan-Out Re-Distribution Layer (InFO-RDL) packaging technique which provides a silicon bridge for high bandwidth and high density die-to-die communication. InFO allows dies to be connected without the use of a more costly silicon interposer such as the one used in AMD's Instinct MI200 and MI300 datacenter accelerators. Each Infinity Fanout link has 9.2 Gbps in bandwidth. Naffziger explains that "The bandwidth density that we achieve is almost 10x" with the Infinity Fanout rather than the wires used by Ryzen and Epyc processors. The chiplet interconnects in RDNA achieve cumulative bandwidth of 5.3 TB/s.

Ray tracing

RDNA 3 features second generation ray-tracing accelerators. Each Compute Unit contains one ray tracing accelerator. The overall number of ray tracing accelerators is increased due to the higher number of Compute Units, though the number of ray tracing accelerators per Compute Unit has not increased over RDNA 2.

Power efficiency

AMD claims that RDNA 3 achieves a 54% increase in performance-per-watt which is in line with their previous claims of 50% performance-per-watt increases for both RDNA and RDNA 2.

RDNA 2

Architectural details

Compute Unit

RDNA 2 contains a significant increase in the number of Compute Units (CUs) with a maximum of 80, a doubling from the maximum of 40 in the Radeon RX 5700 XT.[1] Each Compute Unit contains 64 shader cores. CUs are organized into groups of two named Work Group Processors with 32 KB of shared L0 cache per WGP. Each CU contains two sets of an SIMD32 vector unit, an SISD scalar unit, textures units, and a stack of various caches.[8] New low precision data types like INT4 and INT8 are new supported data types for RDNA 2 CUs.

The RDNA 2 graphics pipeline has been reconfigured and reordered for greater performance-per-watt and more efficient rendering by moving the caches closer to the shader engines. A new mesh shaders model allows shader rendering to be done in parallel using smaller batches of primitives called "meshlets". As a result, the mesh shaders feature enables greater control of the GPU geometry pipeline.

Ray tracing

Real-time hardware accelerated ray tracing is a new feature for RDNA 2 which is handled by a dedicated ray accelerator inside each CU.[10] Ray tracing on RDNA 2 relies on the more open DirectX Raytracing protocol rather than the Nvidia RTX protocol.

In February 2023, it was reported that driver updates had boosted ray tracing performance by up to 40% using DirectX Raytracing.

Clock speeds

With RDNA 2 using the same 7 nm node as RDNA, AMD claims that RDNA 2 achieves a 30% frequency increase over its predecessor while using the same power.

Power efficiency

AMD claims that RDNA 2 achieves up to a 54% increase in performance-per-watt over the first RDNA microarchitecture. 21% of that 54% improvement is attributed to performance-per-clock enhancements, in part due to the addition of Infinity Cache.

RDNA 1

By Fritzchens Fritz, CC0, Link

Architecture

The architecture features a new processor design, although the first details released at AMD's Computex keynote hints at aspects from the previous Graphics Core Next (GCN) architecture being present for backwards compatibility purposes, which is especially important for its use (in the form of RDNA 2) in the major ninth generation game consoles (the Xbox Series X/S and PlayStation 5) to preserve native compatibility with their pre-existing eighth generation game libraries designed for GCN. It features multi-level cache hierarchy and an improved rendering pipeline, with support for GDDR6 memory.

Starting with the architecture itself, one of the biggest changes for RDNA is the width of a wavefront, the fundamental group of work. GCN in all of its iterations was 64 threads wide, meaning 64 threads were bundled together into a single wavefront for execution. RDNA drops this to a native 32 threads wide. At the same time, AMD has expanded the width of their SIMDs from 16 slots to 32 (aka SIMD32), meaning the size of a wavefront now matches the SIMD size.

RDNA also introduces working primitive shaders. While the feature was present in the hardware of the Vega architecture, it was difficult to get a real-world performance boost from and thus AMD never enabled it. Primitive shaders in RDNA are compiler-controlled.

The display controller in RDNA has been updated to support Display Stream Compression 1.2a, allowing output in 4K@240 Hz, HDR 4K@120 Hz, and HDR 8K@60 Hz.

Differences between GCN and RDNA

There are architectural changes which affect how code is scheduled:

1. Single cycle instruction issue
   • GCN issued one instruction per wave once every 4 cycles
   • RDNA issues instructions every cycle
2. Wave32
   • GCN used a wavefront size of 64 threads (work items)
   • RDNA supports both wavefront sizes of 32 and 64 threads
3. Workgroup Processors
   • GCN grouped the shader hardware into "compute units" (CUs) which contained scalar ALUs and vector ALUs, LDS and memory access. One CU contains 4 SIMD16s which share one path to memory.
   • RDNA introduced the "workgroup processor" ("WGP"). The WGP replaces the compute unit as the basic unit of shader computation hardware/computing. One WGP encompasses 2 CUs. This allows significantly more compute power and memory bandwidth to be directed at a single workgroup.